1. Field of the Invention
The present invention relates to a semiconductor device, and a test circuit and a test method for testing a semiconductor device. The present invention more particularly relates to a semiconductor device that treats a serial data inputted synchronously with a spread spectrum clock (SSC), and a test circuit and a test method for testing the semiconductor device.
This application is based upon and claims the benefit of priority from Japanese patent application No. 2007-008424 filed on Jan. 17, 2007, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of Related Art
When a clock generator in an electronic appliance generates a single frequency, radiation of the frequency and harmonic components becomes increased. For this reason, a spread spectrum clock generator is used for performing a frequency modulation on a clock and consequently reducing peaks of the unnecessary radiation and reducing EMI (Electro-Magnetic Interference).
As an example of the spread spectrum clock generator according to a related art, Japanese Laid-Open Patent Application JP-P 2005-4451A (corresponding to US2004252751A1) discloses a spread spectrum clock generator. The spread spectrum clock generator described in JP-P 2005-4451A uses a controller and a phase interpolator and consequently generates a spread spectrum clock without using a voltage controlled oscillator (VCO).
In recent years, as speed of an operation frequency is made higher and skew among bits in a parallel bus becomes severer, a serial interface having no skew among bits becomes popular and is used in a typically usable personal computer (PC) and the like. For example, SATA (Serial Advanced Technology Attachment) is used as the interface standard between a hard disc and CPU. The SATA is the serial interface standard of the first generation with the communication speed of 1.5 Gbps, and includes the standard of the spread spectrum clock as the EMI countermeasure to be used in PC and the like.
A Serializer/Deserializer (SerDes) used in the interface of the standard includes the foregoing spread spectrum clock generator, and a converted serial data is outputted synchronously with the spread spectrum clock. Also, in order to output a parallel data tracking the spread spectrum clock, the deserializer includes a CDR (Clock and Data Recovery) circuit.
As an example of the CDR circuit according to an related art, Japanese Laid-Open Patent Application JP-P 2005-5999A (corresponding to US2004252804A1) discloses a clock and recovery circuit. The CDR circuit described in JP-P 2005-5999A performs a feedback process through a frequency tracking loop and a phase tracking loop on a serial data on which the frequency modulation is performed using the spread spectrum clock. Then, a clock synchronous with the serial data is recovered, Consequently, the CDR circuit described in JP-P 2005-5999A can output a parallel data following the serial data on which the frequency modulation is performed.
On the other hand, as disclosed in Japanese Laid-Open Patent Application JP-P 2005-233933A (corresponding to US2005156586A1), a loop back test is well known as a test method of the SerDes. In the test method described in JP-P 2005-233933A, a pattern data (a parallel data) from a pattern generator is firstly converted into a serial data by a serializer, and the serial data is converted into the parallel data by a deserializer, Next, a pattern comparator compares the pattern data and the converted parallel data and judges the agreement/disagreement.
An operation of a loop back test of a SerDes 300 including a CDR circuit and a SSCG will be described below. FIG. 1 is a block diagram showing a configuration of a test circuit according to a related art. Here, the SerDes 300 is included in an LSI 100 and includes: a deserializer 110 including a CDR circuit 160; and a serializer 12 including a SSCG 17. Also, the LSI 100 includes a pattern generator 13 and a pattern comparator 14, which serve as a loop back test circuit 400. A pattern data 3 outputted by the pattern generator 13 is serial converted by the serializer 12 and outputted as a serial data 4. At this time, the SSCG 17 spectrally-spreads an inputted reference clock signal 1 to generate a spread spectrum clock. The serializer 12 outputs the serial data 4 in synchronization with this spread spectrum clock.
The CDR circuit 160 recovers a synchronous clock from the serial data 4. The deserializer 110 outputs a parallel data 5 converted from the serial data 4 to the pattern comparator 14 in synchronization with a synchronous bit of this serial data 4. The pattern comparator 14 compares the pattern data 3 and the parallel data 5. If the pattern data 3 and the parallel data 5 are coincident, the pattern comparator 14 outputs a judgment signal 6 indicative of “Pass” as a judgment signal 6. If the pattern data 3 and the parallel data 5 are not coincident, the pattern comparator 14 outputs a judgment signal indicative of “Fail” as the judgment signal 6. Such a loop back test can be used to test a clock data recovery performance of the CDR circuit 160.
We have now discovered the following fact. FIGS. 2A and 2B are examples of timing charts in the loop back test according to the related art. The drawings show the judgment results of the loop back test when the CDR circuit 160 is normally operated. FIG. 2A shows the modulation deviation profile of the spread spectrum clock, the frequency limit value (SSC tolerance lower limit value) that can be tracked by the CDR circuit 160, and the Pass/Fail judgment signal 6, when the SSCG 17 is normally operated. FIG. 2B shows the modulation deviation profile of the spread spectrum clock, the frequency limit value (SSC tolerance lower limit value) that can be tracked by the CDR circuit 160, and the Pass/Fail judgment signal 6, when the SSCG 17 is abnormally operated.
With reference to FIG. 2A, when the SSCG 17 is normally operated, the modulation deviation of the spread spectrum clock is equal to or higher than the SSC tolerance lower limit value of the CDR circuit 160. Thus, the CDR circuit 160 can carry out the clock data recovery. Hence, as long as the CDR circuit 160 is normally operated, the pattern comparator 14 outputs a Pass signal.
With reference to FIG. 2B, even if the SSCG 17 is abnormal and the generated spread spectrum clock does not indicate a desirable modulation deviation, when the modulation deviation is equal to or higher than the SSC tolerance lower limit value of the CDR circuit 160, the CDR circuit 160 can carry out the clock data recovery. In this case, the Pass signal is outputted similarly to the foregoing case. That is, independently of the normal or abnormal state of the SSCG, the CDR circuit 160 normally carries out the clock data recovery, and the pattern comparator outputs the signal indicative of “Pass”. For this reason, a tester 200 cannot detect the abnormality of the SSCG 17.
Also, although not shown in the drawings, when the SSCG 17 generates the spread spectrum clock at the modulation deviation exceeding the SSC tolerance of the CDR circuit 160 according to the abnormal operation, the CDR circuit 160 cannot carry out the clock data recovery. Thus, the pattern comparator 14 outputs the Fail signal. In this case, the tester 200 cannot point out whether the CDR circuit 160 is abnormal, or the SSCG 17 is abnormal, or both are abnormal.
Thus, the loop back test according to the related art cannot detect the abnormality of the SSCG included in the SerDes. Moreover, even if the CDR circuit is troubled and the SSC tolerance lower limit value is deviated from the desirable values when the modulation deviation of the spread spectrum clock is equal to or higher than this lower limit value, namely, when this exhibits the result as shown in FIG. 2B, it is impossible to detect not only the abnormality of the SSCG, but also the abnormality of the SSC tolerance of the CDR circuit. Thus, this leads to the quality decrease of the product.